1. Field of the Invention
The present invention relates generally to a scan driver for an organic light emitting display, and more particularly to a scan driver configured to of freely adjust the widths of emission control signals, an organic light emitting display employing the scan driver, and a method of driving the organic light emitting display.
2. Discussion of Related Technology
Various flat panel displays have been developed with reduced weight and volume to overcome the disadvantages of cathode ray tube (CRT) displays. Exemplary types of flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and organic light emitting displays.
An organic light emitting display is a spontaneous emission device that emits light by re-combination of electrons and holes. Organic light emitting displays have a high response speed and are driven with low power consumption. An exemplary organic light emitting display supplies currents corresponding to data signals to an organic light emitting diode using transistors formed in each pixel, such that light is emitted from the organic light emitting diode in response to the supplied currents.
Exemplary organic light emitting displays include a scan driver for selecting pixels and controlling the luminescence of the pixels, and a data driver for supplying the data signals to the selected pixels. The scan driver selects the pixels to which the data signals are to be supplied while sequentially supplying scan signals to scan lines. The scan driver also sequentially supplies emission control signals to emission control lines so as to control the emission time of the pixels.
FIG. 1 is an electrical schematic of an exemplary scan driver 5. The scan driver 5 comprises a shift register 10 and a signal generator 20. The shift register 10 is configured to sequentially shift a start pulse SP, supplied from outside the scan driver 5, in response to a clock signal CLK so as to generate sampling pulses. The signal generator 20 is configured to generate scan signals and emission control signals in response to the sampling pulses, supplied from the shift register 10, and an output enable signal OE, which is supplied from outside the scan driver 5.
The shift register 10 comprises n (where n is an integer) D flip-flops. The D flip-flops DF1 to DFn are driven when the clock signal CLK and the sampling pulses (or the start pulse) are supplied from the outside. In the illustrated scan driver 5, odd D flip-flops (e.g., DF1, DF3, . . . ) are driven at the rising edge of the clock signal CLK and even D flip-flops (e.g., DF2, DF4, . . . ) are driven at the falling edge of the clock signal CLK. Thus, in the exemplary shift register 10, D flip-flops driven at the rising edge of the clock signal CLK and D flip-flops driven at the falling edge of the clock signal CLK are alternately arranged.
The signal generator 20 comprises a plurality of logic gates. In the illustrated scan driver 5, the signal generator 20 includes a NAND gate for each scan line S and a NOR gate for each emission control line E. Thus, the signal generator 20 includes n NAND gates and n NOR gates.
A NAND gate NANDi, connected to an ith scan line Si (wherein i is an integer), is driven by the output enable signal OE, the sampling pulse of the ith D flip-flop DFi, and the sampling pulse of the (i−1)th D flip-flop DFi−1. In the illustrated scan driver, the output of the NAND gate NANDi is supplied to the ith scan line Si through at least one inverter IN and buffer BU in series.
The NOR gate NORi, connected to the ith emission control line Ei, is driven by the sampling pulse of the (i−1)th D flip-flop DFi−1 and the sampling pulse of the ith D flip-flop DFi. In the illustrated scan driver, the output of the NOR gate NORi is supplied to the ith emission control line Ei through at least one inverter IN.
FIG. 2 is an illustration of exemplary waveforms illustrating a method of driving the scan driver 5. According to an exemplary method of driving the scan driver 5, first, the clock signal CLK and the output enable signal OE are supplied from outside the scan driver. In the exemplary method, a period of the output enable signal OE is half (½) of a period of the clock signal CLK. The high state voltages of the output enable signal OE overlap the high state voltages of the clock signal CLK. The low state voltages of the output enable signal OE overlap the clock signal CLK transitions between high and low state voltages. The output enable signal OE controls the width of scan signals SS. In the exemplary method, the scan signals SS are generated to have the same pulse width as the high voltage state pulse widths of the output enable signal OE.
When the clock signal CLK is supplied to the shift register 10 and the output enable signal OE is supplied to the signal generator 20, the start pulse SP is supplied to the shift register 10 and the signal generator 20 from outside the scan driver 5. More particularly, the start pulse SP is supplied to a first D flip-flop DF1, a first NOR gate NOR1, and a first NAND gate NAND1. The first D flip-flop DF1 that receives the start pulse SP is triggered at the rising edge of the clock signal CLK to generate a first sampling pulse S1. The first sampling pulse S1 is supplied to the first NAND gate NAND1, the first NOR gate NOR1, a second NAND gate NAND2, and a second D flip-flop D2.
The first NAND gate NAND1 receives the start pulse SP, the first sampling pulse S1, and the output enable signal OE, and outputs a low voltage (that is, logic low state of 0) when the start pulse SP, the first sampling pulse S1, and the output enable signal OE have high voltages (that is, logic high state of 1). For other input signal combinations, the first NAND gate NAND1 outputs a high state voltage. In the exemplary method, the first NAND gate NAND1 outputs a low state voltage during a portion of the duration of the first sampling pulse S1. The low voltage output from the first NAND gate NAND1 is supplied to the first scan line S1 via a first inverter IN1 and a first buffer BU1. The first scan line S1 supplies the low voltage from the first buffer BU1 as the scan signal SS to the pixels.
The first NOR gate NOR1 receives the start pulse SP and the first sampling pulse S1, and is configured to output a high state voltage when the start pulse SP and the first sampling pulse S1 have low state voltages, and to output a low state voltage in other cases. In the exemplary method, the first NOR gate NOR1 outputs a low state voltage when one of the start pulse SP and the first sampling pulse S1 has a high state voltage. The low voltage output from the first NOR gate NOR1 is changed to a high state voltage via the second inverter IN2 to be supplied to the first emission control line E1. The high voltage at the first emission control line E1 as an emission control signal EMI is also supplied to the pixels.
In the exemplary method, the scan driver 5 sequentially supplies the scan signals SS to the 1st through nth scan lines S1 to Sn, respectively, while repeating the above-described processes. Also, the scan driver 5 sequentially supplies the emission control signals EMI to the 1st through nth emission control lines E1 to En, respectively, while repeating the above-described processes. The scan signals SS sequentially select the pixels and the emission control signals EMI control the emission time of the pixels.
In an organic light emitting display employing the scan driver 5 described above, the brightness of the pixels is controlled only by freely controlling the width of the pulse of the emission control signals EMI regardless of the scan signals SS. However, according to the prior art, when the width of the pulse of the emission control signals EMI is set wide (i.e., long duration), desired scan signals SS are not generated.
Specifically, in order to set the width of the pulse of the emission control signals EMI wide, the width of the start pulse SP must be set wide as illustrated in FIG. 3. When the width of the start pulse SP is set wide, the first NOR gate NOR1 performs a logic NOR operation on the outputs of the start pulse SP and the first D flip-flop DF1 to set the width of the generated emission control signals EMI. However, when the width of the start pulse SP is set wide, undesired scan signals SS are generated.
Because the scan signals SS are generated when the start pulse SP, the first sampling pulse S1, and the output enable signal OE have high state voltages, the first NAND gate NAND1 outputs a plurality of low voltages in response to a wide width of the start pulse SP. When the width of the start pulse SP overlaps the three periods of the clock signal CLK, the first NAND gate NAND1 outputs three low voltages as illustrated in FIG. 3. Thus, according to the prior art, when the width of the start pulse SP is set wide, the width of the emission control signals EMI is set no less than two periods of the clock signal CLK since the plurality of scan signals SS are supplied to the scan lines S, respectively. Thus, an improved method of setting the width of emission control signals pulse is needed in the technology.